Introduction
The Digital Autonomy with RISC-V in Europe, DARE project is a program to build European processors for high performance computing (HPC) and artificial intelligence (AI) based on the open RISC-V processor architecture.
Project Objectives and Coordination
The DARE SGA1 project is the first phase of this program aimed at strengthening Europe's technological sovereignty in HPC and AI computing. The project is supported by the EuroHPC JU and coordinated by the Barcelona Supercomputing Center, with the participation of 37 leading partners from across Europe. The project involves the development of next-generation European processors and computing systems. Part of the work will also include a system software ecosystem as well as dedicated RISC-V architecture versions of scientific software packages.
Key Hardware Components of the Project
A key component of the DARE SGA1 project is the development of three RISC-V-based chiplets, each with a critical function in HPC and AI computing:
- a vector accelerator (VEC) for high-precision HPC and new applications in the HPC-AI convergence domain, led by Openchip;
- AI processing unit (AIPU) designed to accelerate AI inference in HPC applications, led by Axelera AI;
- a general purpose processor (GPP) optimized for HPC workloads in European supercomputers, led by Codasip. Chiplets will be developed and manufactured using advanced CMOS technologies, overcoming the limitations of traditional monolithic chips, offering greater performance, scalability and higher cost advantages.
Parallel Software Development
To ensure the success of these innovations, DARE SGA1 will simultaneously deliver an optimised and complete software stack optimized for DARE SGA1 hardware. The software will be built in parallel with the hardware design, taking advantage of early access to emulation and simulation architectures.
Participation of Cyfronet
In the DARE SGA 1 project, ACC Cyfronet AGH brings competences in the field of adapting applications to processor architectures. Cyfronet will support the project partners in adapting the PyTorch software to the architecture of processors developed by the project. Also Polish LLM models will be tested on processors dedicated to artificial intelligence.
More Information
Visit the project website.
PROJECT CO-FUNDED BY THE NATIONAL CENTRE FOR RESEACH AND DEVELOPMENT UNDER THE EUROHPC JOINT UNDERTAKING PROGRAM