---
title: 'The DARE Project - on the way to digital autonomy for Europe in HPC and AI'
url: 'https://www.cyfronet.pl/en/news/2025/the-dare-project-on-the-way-to-digital-autonomy-for-europe-in-hpc-and-ai'
markdown: 'https://www.cyfronet.pl/en/news/2025/the-dare-project-on-the-way-to-digital-autonomy-for-europe-in-hpc-and-ai.md'
lang: en
date: '2025-03-07'
description: 'The Digital Autonomy with RISC-V in Europe, DARE project is a program to build European processors for high-performance computing (HPC) and artificial intelligence (AI) based on the open RISC-V processor architecture. The DARE SGA1 project is the first phase of this program aimed at strengthening …'
taxonomy:
  type:
    - news
  tag:
    - 'EuroHPC JU'
    - DARE
    - RISC-V
  filtering:
    - ai
    - cooperation
    - science
---

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# The DARE Project - on the way to digital autonomy for Europe in HPC and AI

Publication date: March 7, 2025

**The Digital Autonomy with RISC-V in Europe, DARE project is a program to build European processors for high-performance computing (HPC) and artificial intelligence (AI) based on the open RISC-V processor architecture.**

The DARE SGA1 project is the first phase of this program aimed at strengthening Europe's technological sovereignty in HPC and AI. The project is supported by the EuroHPC JU Joint Undertaking and coordinated by the Barcelona Supercomputing Center, with the participation of 37 leading partners from all over Europe. 

The project aims to develop next-generation European processors and computing systems. Part of the work will also include an ecosystem of system software and RISC-V versions of scientific software packages. 

A key element of the DARE SGA1 project is the development of three RISC-V-based chiplets, each of which plays a critical role in HPC and AI computing:

- A vector accelerator (VEC) for high-precision HPC and new applications in the HPC-AI convergence domain, led by Openchip
- An AI processing unit (AIPU) designed to accelerate AI inference in HPC applications, led by Axelera AI
- A general-purpose processor (GPP) optimized for HPC workloads in European supercomputers, led by Codasip

The chiplets will be designed and manufactured in advanced CMOS technologies, overcoming the limitations of traditional monolithic chips, offering higher performance, scalability, and higher cost benefits. 

To ensure the success of these innovations, DARE SGA1 will simultaneously deliver an optimal and complete software stack, optimized for the DARE SGA1 hardware. The software will be built in parallel with the hardware design, using early access to architecture emulation and simulation. 

The Academic Computer Center Cyfronet AGH brings to the project competences in the field of adapting applications to processor architectures. Cyfronet will support the project partners in adapting the PyTorch software to the architecture of processors developed by the project. In parallel, Polish LLM models will be tested on processors dedicated to artificial intelligence. 

 We invite you to read the [full press release on the project website](https://dare-riscv.eu/launch-of-dare-sga1-project/).

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